Digital Design Engineer Apprenticeship
Synopsys — Noida, Uttar Pradesh
₹4–9 LPA (HireSetu estimate) · Entry level · 2026 batch · Full-time
HireSetu listing reference a263ce — confirm requirements below, then apply on the employer site.
Quick answer: A 12-month, in-office apprenticeship in Noida writing UVM testbenches for the digital blocks of Serdes PHYs. It is open only to 2025 and 2026 bachelor's graduates who have not started an M.Tech or a full-time job, and the start date is November 2026.
From Synopsys's job posting
We Are
Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.
Apprenticeship Experience
At Synopsys, Apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide and having fun in the process. You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!
What You'll Be Doing
- Assist in developing and maintaining UVM-based testbenches for functional verification of digital blocks of Serdes PHYs
- Create and execute test cases, sequences, checkers, and assertions to verify RTL functionality and ensure protocol compliance in Serial Links.
- Analyze simulation results, debug test failures, and work closely with design engineers to identify and resolve functional issues.
- Contribute to coverage-driven verification by developing functional coverage models and tracking verification metrics to improve design quality.
What You'll Need
- Completed Bachelor's degree in Electronics and Communication Engineering, Electrical or a related field (Mandatory).
- Fresh graduates from the class of 2026 or 2025.
- Not currently enrolled / completed any M-Tech programs or postgraduate diplomas.
- Not employed in any full-time positions at any company (limited internship experience is acceptable).
- Strong digital electronics fundamentals.
- Proficiency in Verilog and SystemVerilog, you have written RTL/Testbenches.
- Exposure to functional verification methodologies like UVM, OVM, or VMM is a plus.
- Theoretical knowledge of protocols such as PCIe is a plus.
Key Program Facts:-
- Program Length: 12 months Apprenticeship Program
- Location: Noida, India
- Working Model: In office
- Full-Time/Part-Time: Full-time
- Start Date: November 2026
The employer’s company overview, benefits and equal-opportunity statement are left out here; they are on the original posting.
Text from Synopsys's official job posting, formatted by HireSetu. The employer's own page is the final word on details.
HireSetu's note
The eligibility list is the real filter
The rules are tight and self-declared: a bachelor's in electronics and communication, electrical or something close; graduating in 2025 or 2026; no M.Tech or postgraduate diploma begun or finished; and no full-time job on your record. Internships are fine. If you have enrolled in a master's or joined a company full-time, this one is closed however good your Verilog is.
Note the start date: November 2026. If you graduate mid-2026, there is a stretch before the apprenticeship begins, so decide whether that gap suits you before you apply.
Lead your resume with written RTL and testbenches
The listing asks for proficiency in Verilog and SystemVerilog and says you have written RTL or testbenches, so a project where you actually built and ran one outranks a high CGPA. Put the verification project first: what the DUT was, how you drove stimulus, what you checked, what failed.
UVM, OVM or VMM exposure is listed as a plus, and PCIe theory as another. Both deserve a line if you have them, and both are learnable, since everyone applying is a fresher. Digital fundamentals are the other stated requirement, and they matter as much as the tooling.
Groundwork worth doing
For verification work of this kind, the useful revision is SystemVerilog beyond plain Verilog: classes, constrained random stimulus, functional coverage and assertions. On the UVM side, know the component roles and phases, how a sequence reaches a driver, and what a scoreboard does with a monitor's output.
Serial links are the domain. Build a working picture of a SerDes PHY, why serializers and equalization exist, and what an eye diagram shows. PCIe basics, lanes and link training, are enough to follow a conversation. Get comfortable in a waveform viewer too, since debugging a failing simulation is a large part of this work.
Drafted with AI from Synopsys's job posting and checked by Prashanth Jakkula before publishing. See our Editorial Policy.
How to apply
- Open Synopsys's careers site with the Apply button.
- Follow the application steps on the site and upload your resume.
- Keep the confirmation email or application number for follow-up.
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