Staff Memory Circuit Design Engineer
Broadcom — Bangalore, Karnataka
₹4–8 LPA (HireSetu estimate) · Full-time · onsite · Apply by 15 Feb 2027
HireSetu listing reference 4b33ba · employer requisition R026828 — confirm requirements below, then apply on the employer site.
Quick answer: Work on memory compilers and custom macros in Broadcom's Central Engineering group in Bangalore, at the transistor and gate level. The Staff title sits above a listing that openly has room at every experience level, so depth in device behaviour and post-layout work is the real filter.
From Broadcom's job posting
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Job Description
We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.
Available Job Responsibilities
Design and build memory or circuit blocks at the gate or transistor level
Simulate and analyze the circuit design using transistor level simulators
Extract the layout and perform post-layout simulations and verification
Floorplan physical implementation and layout integration of design components
Integrate characterization flow to extract timing and power information
Develop scripts to automate characterization flow, simulations, and verification
Specify and verify various behavioral and physical memory models
Document the design specifications, behavioral description, and timing diagrams
Help specify silicon test plan and correlate silicon to simulation data
Preferred Skills
Good understanding of transistor level circuit behavior and device physics
Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
Proficiency in running simulators, writing automation scripts, and are tools savvy
Understanding of memory behavioral and physical models is a plus
Expertise in memory circuit design is a plus
Understanding of DFT schemes and chip level integration is a plus
Motivated, self-driven and good at multi-tasking
Passion for solving complex problems and willingness to learn
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
The employer’s company overview, benefits and equal-opportunity statement are left out here; they are on the original posting.
Text from Broadcom's official job posting, formatted by HireSetu. The employer's own page is the final word on details.
HireSetu's note
Senior title, wide ladder
The posting carries a Staff title and says in the same breath that there are multiple openings at all experience levels. That reads as a team being built out around memory compilers and custom macros, not one slot with a rigid bar. A few years of custom or analog circuit work, with post-layout or silicon experience behind you, puts you in range. Freshers with only coursework will find the responsibilities list unforgiving.
The block is judged after extraction
Schematic design is the start. Extraction, post-layout simulation and verification, floorplanning and layout integration are core duties, so the circuit gets judged once parasitics are in. Signal integrity, EM/IR and reliability analysis sit next to the timing and power numbers you produce. Revise sense amplifier offset, bitcell read and write margins, Monte Carlo across process variation, and what IR drop does to a memory array. Device physics underlies all of it.
Automation is the deliverable
Memory compilers exist to produce many variants, so characterization, simulation and verification flows get scripted. The role includes writing that automation, generating timing and power views across corners, and keeping the flows alive as the process shifts. The silicon correlation duty closes the loop: input into the test plan, then matching measured data against simulation. Foundation IP means you follow a block from schematic to layout to silicon, and repeat the whole cycle at the next node.
Drafted with AI from Broadcom's job posting and checked by Prashanth Jakkula before publishing. See our Editorial Policy.
How to apply
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