DFX RTL Design Engineer

AMD — Hyderabad

₹8–24 LPA (HireSetu estimate) · Entry level · Freshers eligible · Full-time · onsite · Apply by 19 Aug 2027

HireSetu listing reference 6ae947 — confirm requirements below, then apply on the employer site.

Quick answer: The gate here is hands-on DFX implementation: scan, JTAG, boundary scan, debug features, and low power with UPF. RTL design is the medium, but the team assumes you have already built this infrastructure on a real chip programme.

From AMD's job posting

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE

We are looking for an adaptive, self-motivative DFX RTL design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The DFX Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON

Be a member of the Client SOC DFX team that plays a significant role in ensuring the quality of next generation microprocessors through structured DFX Architecture and edge cutting DFX techniques. You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

  • DFX Design Planning and Implementation of DFX Features like JTAG, Scan, Boundary Scan, Debug features etc.
  • Handling Low Power features and UPF support.
  • Work with CAD, IP team for requirements and implementation and power scenarios.
  • Work with DFX Verification team for Quality.
  • Active involvement in DFX Initiatives and process Development
  • Provide technical support to other cross functional teams
  • Need to be a team player and work Collaboratively with team members

PREFERRED EXPERIENCE

  • In-depth knowledge of DFX Features.
  • Hands on experience on DFX implementation, low power technologies.
  • Experience with latest Scan/MBIST architecture is a benefit
  • Familiarity with Verilog, VCS, SystemVerilog, VHDL etc...
  • Should be Good at C/C++, Python, Perl, TCL and other scripting languages.
  • Experience/Background on Computing/Graphics is a benefit
  • Work experience in a medium to large team making impact to the team members.

ACADEMIC CREDENTIALS

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-AA1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

Text from AMD's official job posting, formatted by HireSetu. The employer's own page is the final word on details.

HireSetu's note

The gate is DFX implementation

Writing Verilog for a block is the easy half. This team builds the test and debug fabric that spans a client SOC: scan chains, JTAG and boundary scan, on-chip debug, and the power intent that carries all of it across UPF domains. In-depth DFX knowledge and hands-on implementation are the ask, so the strongest candidates have taken a feature through RTL, integration and silicon bring-up.

Put the DFX blocks first on your CV

Lead with the specific work: scan insertion and stitching, a JTAG TAP or boundary scan RTL, MBIST architectures, UPF power intent, debug logic. Name the block, the feature and the flow you ran. The tools matter because the list is long: Verilog and SystemVerilog for design, VHDL alongside, scripting in Python, Perl, TCL and C/C++. That spread points to a fair amount of automation and flow work around the design itself, so a script you wrote that saved your team hours earns a line.

Hard filters and extras

The degree is a hard filter: computer engineering or electrical engineering, bachelor's or master's. Hands-on DFX implementation and low power come next. The extras are the newest scan and MBIST architectures, a computing or graphics background, and VHDL. The posting leaves seniority open, so the depth of your DFX work settles where you land. Worth confirming how the Hyderabad team splits work with engineers in other sites and timezones, and whether you own a feature end to end or a slice of one.

Experience decides this one

Nothing here points to a graduate hire. The posting describes sitting with CAD, IP and verification teams on requirements, implementation and power scenarios, which is work for an engineer who has shipped at least one DFX feature and knows where it tends to break. A fresher with strong digital design coursework is a long shot.

Drafted with AI from AMD's job posting and checked by Prashanth Jakkula before publishing. See our Editorial Policy.

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