CPU Verification Engineer – Core Enablement
AMD — Bengaluru, Karnataka
₹5–10 LPA (HireSetu estimate) · Fresher-friendly · Full-time
HireSetu listing reference 877710 — confirm requirements below, then apply on the employer site.
Quick answer: IP-level verification of AMD's graphics processor IP in Bengaluru. You build UVM testbenches, run directed and random tests, and chase failures down to root cause with RTL and firmware engineers until coverage closes. The preferred list reads like a working verification engineer's CV.
From AMD's job posting
THE ROLE
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.
THE PERSON
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
PREFERRED EXPERIENCE
- Proficient in IP level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Graphics pipeline knowledge
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux with exposure to Windows platform
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assets with prior exposure to video codec system or other multimedia solutions.
ACADEMIC CREDENTIALS
- Bachelors or Masters degree in computer engineering/Electrical Engineering
- #LI-BM2
Text from AMD's official job posting, formatted by HireSetu. The employer's own page is the final word on details.
HireSetu's note
Which silicon you'd actually verify
The title points at Core Enablement and CPU verification, while the responsibilities describe verifying features on AMD's graphics processor IP. Graphics pipeline knowledge and video codec or multimedia exposure are listed as assets too. Treat it as a graphics team role sitting under a broader team name.
If your background is CPU cores, caches or coherency, the UVM and debug habits carry over but the domain is new, and the graphics pipeline takes real time to learn. Ask which IP block and which feature area you'd own.
The profile behind that preferred list
Developing UVM frameworks, flows and testbenches. SystemC and TLM. HLS tools. Scripting in Perl, Ruby, Makefile or shell. Automating jobs across a distributed compute farm, with strong C++ on Linux. Put together, that is someone two to five years into IP verification, ideally on graphics or another complex block.
A fresh master's with serious SystemVerilog and UVM project work is not out of the running, but the comparison set is people who have closed coverage on chips that shipped. Coursework directed tests are a different exercise from building and maintaining a framework other engineers write tests against.
Debugging in simulation is the whole day, and the listing is honest about it: test failures, root cause, arguments with RTL and firmware owners about where the defect lives. Have one failure you traced to its source ready to describe plainly, what looked wrong at first, where it ended up, and what the fix was.
Drafted with AI from AMD's job posting and checked by Prashanth Jakkula before publishing. See our Editorial Policy.
How to apply
- Open AMD's careers site with the Apply button.
- Follow the application steps on the site and upload your resume.
- Keep the confirmation email or application number for follow-up.
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