Mixed-Signal Systems and Verification Engineer
Cadence — Bengaluru, Karnataka
₹15–18 LPA (HireSetu estimate) · 0–1 yrs exp · Freshers eligible · Full-time · onsite · Apply by 25 Dec 2026
HireSetu listing reference d0d0aa · employer requisition R55855 — confirm requirements below, then apply on the employer site.
Quick answer: An entry-level mixed-signal verification job in Bengaluru where the real gate is writing real-numbered behavioural models in SystemVerilog. You are not being hired to design analog circuits, you are being hired to model and check them.
From Cadence's job posting
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Qualifications • New graduates strongly encouraged to apply!
• Experience in developing and verifying real-numbered behavioral models in SystemVerilog • Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS • Basic understanding of AMS blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc • Working experience in low power Architecture • Working experience in Cadence Virtuoso Schematic Composer and ADE • Experience with Analog Assertion Based Verification • Experience in TB development will be a strong plus • Experience in writing scripts in languages such as Perl or Python • Excellent teammate with excellent communication skills • Experience with FPGA prototyping is a plus Responsibilities • You will become part of a hands-on development team that fosters engineering excellence, creativity, and innovation.
• As an AMS Verification Engineer, you will be responsible for Developing accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog. • Verifying that the behavior models are accurate representations of analog schematics • Integrating the models with RTL • Verifying analog functionalities against design specifications using analog behavioral models: for example, coding test benches, test scenarios, and assertions. • DSP experience a huge plus.
Documenting modeling and verification results for formal review We’re doing work that matters. Help us solve what others can’t
Text from Cadence's official job posting, formatted by HireSetu. The employer's own page is the final word on details.
HireSetu's note
Two skills carry the weight
Real-numbered modelling in SystemVerilog is the first. That means wreal, RNM, UDN/UDT/UDR and Verilog-AMS: writing a model of an analog block that simulates quickly and still behaves like the circuit. The second is Virtuoso Schematic Composer and ADE. You will be checking models against real schematics, so you have to open one and trace it.
Most freshers arrive with one of these and not the other. SystemVerilog coursework without Virtuoso is common, and so is the reverse from an analog elective. Both gaps are closable, but know which one is yours.
Digital habits only go so far
UVM agents, coverage-driven random stimulus, reference models in SystemVerilog: none of that is the centre of this role. Here the testbench drives analog behaviour and the checks read like settling, gain, lock time, jitter, written as analog assertions. Testbench development is listed as a strong plus, so building them counts, at the AMS layer.
The block list in the posting, filters, ADC, DAC, VCO, PLL, SerDes, LNA, mixer, is the vocabulary the team speaks every day. If those names mean nothing beyond a textbook diagram, brush up on what each one does before you apply.
The block decides your day
Ask which blocks and which group you would land in. Modelling a SerDes and modelling a data converter are different jobs with different simulation runtimes and different failure modes. Ask how the work splits between building models and verifying them, and which simulator and flow the team runs.
Low power architecture appears in the requirements, which is a stretch for freshers who haven't touched it. Find out what it means in this team's context instead of guessing.
Drafted with AI from Cadence's job posting and checked by Prashanth Jakkula before publishing. See our Editorial Policy.
How to apply
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- Upload your resume and check every auto-filled field; Workday often misreads dates and job titles.
- Answer the screening questions, submit, and look for the confirmation email from Workday.
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