System Validation Engineer
SiFive — Hsinchu, Taiwan
₹4–8 LPA (HireSetu estimate) · Entry level · Freshers eligible · Full-time · onsite
HireSetu listing reference 938c6d · employer requisition R-101316 — confirm requirements below, then apply on the employer site.
Quick answer: An entry-level seat on SiFive's RISC-V system validation team, working on FPGA-based CPU platforms and development boards. Two things decide whether this is worth your time: Verilog taken onto an FPGA and Linux scripting are required, and the offer is tied to proof of your right to work in Taiwan.
From SiFive's job posting
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
The Role
The successful candidate will join SiFive's System Validation team, which is responsible for the validation of SiFive's RISC-V CPUs utilizing FPGA-based platforms. This role extends beyond FPGA platforms to include development and bring-up boards.
This position offers significant exposure to RISC-V processors, the RISC-V software ecosystem, and various development boards, providing exceptional learning opportunities for engineers pursuing a career in the RISC-V domain.
Responsibilities
- Execute root cause and failure analysis across RISC-V CPU hardware and software components.
- Utilize ILA and JTAG debuggers to troubleshoot and validate FPGA designs.
- Develop failure hypotheses through systematic, step-by-step elimination of potential causes.
- Create and support Python-based scripts to enhance and automate debug workflows.
Requirements
- A Bachelor’s or Master’s degree in Computer Science or Electronics and Communication Engineering is required.
- A strong comprehension of Computer Architecture and logic design is essential.
- Prior exposure to logic design using Verilog and the subsequent porting of designs onto FPGA platforms is necessary.
- Practical experience with Linux-based operating systems and scripting languages such as Python and BASH is mandatory.
- Candidates must possess a positive attitude, a proactive approach to continuous learning, and a commitment to achieving excellence in their work.
Additional Information
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
Taiwan
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Text from SiFive's official job posting, formatted by HireSetu. The employer's own page is the final word on details.
HireSetu's note
The work permit question comes first
The location line reads Hsinchu and Bengaluru, but the additional information pins the offer to proof of right to work in Taiwan, plus background and reference checks and export-control screening. Ask which site the headcount actually sits in, and whether Bengaluru is a live second option or leftover text from a wider posting. Export screening is routine for CPU work and can add weeks between offer and start date.
If you would need a Taiwan visa, settle that early. It runs alongside the technical steps, not after them.
Architecture you can reason with
Verilog that has been through synthesis and onto an FPGA is the baseline, and computer architecture is the lens you debug through. Expect working knowledge of pipelines, caches, memory ordering, interrupts and privilege modes, plus how blocks talk to each other over a bus. Simulation passing is a low bar. Bring-up adds clocking, reset and timing faults that only show on a board.
ILA and JTAG are how you see inside a running design. If your experience stops at simulation, an evening on triggers and capture buffers is time well spent. Python and BASH exist here to automate the repetitive parts of that loop, so have one small log-parsing script you can talk through.
One bug can eat a week
The responsibilities describe failure analysis as step-by-step elimination: form a hypothesis, rule it out, form the next one. That is the texture of the job, and it is slow. A hang on a bring-up board can take days and end in a two-line fix to a reset sequence. Staying organised about what you have already ruled out matters more than moving fast.
Your output is a root cause and the evidence behind it, then a script or a patch so the next person gets there quicker. Two years of this puts you close to CPU verification, silicon bring-up and the RISC-V software stack, which is useful ground if you want to stay in processors.
Drafted with AI from SiFive's job posting and checked by Prashanth Jakkula before publishing. See our Editorial Policy.
How to apply
- Open SiFive's careers site with the Apply button.
- Create a Workday account for SiFive. Workday logins are separate for every company, so an account made for another employer won't work here.
- Upload your resume and check every auto-filled field; Workday often misreads dates and job titles.
- Answer the screening questions, submit, and look for the confirmation email from Workday.
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