Physical Design Engineer, Associate

HireSetu's note

Where the work sits in the flow

Physical design begins once the RTL is written. You take a synthesised netlist and carry it through floorplanning, placement, clock tree synthesis, routing, timing closure and physical verification until the block hits its power, performance and area targets. The Associate title points at a block or sub-block, with someone senior holding full-chip signoff.

Qualcomm's ASICS group designs chips for the company's own products, so the blocks you touch end up in shipped silicon. Treat this as an on-site, full-time role in Hyderabad and plan where you live around the office.

Fundamentals carry the screening

No experience range, degree or tool list appears in the posting, which is normal for associate openings at large chip companies. The work itself needs static timing analysis, CMOS and standard cell basics, setup and hold, clock skew, and a working grip on Tcl, with Python close behind. Parsing a timing report with a short script is something you would do most weeks.

The one detail worth confirming early is which stage you would own. Placement and routing, timing closure, and physical verification all sit under this title but fill a day very differently.

Most of the hours go into debugging

Newcomers picture this job as feeding a design to a tool and waiting for a clean result. Most of the day is spent in log files and reports, working out why a path misses timing, why a region is congested, or what caused a DRC, then changing a constraint or a floorplan and running it again. The first fix rarely holds.

Near a tapeout the schedule is set by the database being signed off, so some weeks run long and unpredictable. That rhythm is built into the job.

Drafted with AI from Qualcomm's job posting and checked by Prashanth Jakkula before publishing. See our Editorial Policy.