Associate Engineer (ASICS Engineering)

HireSetu's note

Revision worth doing

ASIC work at this level starts from the same base wherever you sit: combinational and sequential logic, state machines, setup and hold, clock domain crossing, FIFO depth. If you can sketch a synchroniser and explain the two flops inside it, you're on solid ground.

Verilog or SystemVerilog is the working language. Reading a testbench and a waveform matters as much as writing RTL, because debugging someone else's block is most of a junior engineer's week. CMOS fundamentals, gate delay and power, come up in any conversation about why a design is slow.

Then static timing analysis: slack, critical paths, constraints, the difference between a real path and a false one. Add one scripting language, Python or Tcl, since chip flows are glued together with scripts.

The sub-team decides your day

The ASICS group covers RTL design, functional verification, synthesis, physical design and DFT, along with the modelling and library work that holds them together. An associate engineer starts in one of those areas at block level, with a senior engineer reviewing the output.

Which one you land in shapes the next two years more than the title does. Design and verification people swap sides early in their careers, and physical design draws heavily on the same digital basics. Ask which sub-team and which chip family you'd sit with; the answer tells you which tools you'll spend your days in.

A degree project that touched RTL, verification or timing gives you something concrete to walk through. A small processor, an AXI block or a FIFO is enough, as long as you can explain your decisions and what broke.

Drafted with AI from Qualcomm's job posting and checked by Prashanth Jakkula before publishing. See our Editorial Policy.