Engineer – AI/ML
Quest Global — Noida, Uttar Pradesh
₹3–7 LPA (HireSetu estimate) · Entry level · Freshers eligible · Full-time
HireSetu listing reference 8d3a97 · employer requisition P-124245 — confirm requirements below, then apply on the employer site.
Quick answer: A Noida role where the work is scripting, data validation and workflow automation around chip design and verification. You need working C/C++ plus a basic grip on Verilog, SystemVerilog, UVM and bus interfaces such as AXI, APB and UART.
From Quest Global's job posting
Job Requirements
- Developing software and automation solutions for engineering workflows
- Programming/scripting using C/C++ or similar languages
- Data processing, validation, reporting and workflow automation
- Working with Linux and engineering tools
- Using AI-assisted tools for test generation, analysis, debugging and documentation
- Basic knowledge of Verilog/SystemVerilog and RTL/DV
- Supporting test cases, simulation and debugging
- Basic understanding of UVM and interfaces such as AXI, APB and UART
- Good analytical, problem-solving and documentation skills
Text from Quest Global's official job posting, formatted by HireSetu. The employer's own page is the final word on details.
Scripts and logs fill the week
The requirements read like a day plan: writing software that drives engineering workflows, processing and validating data, then reporting what came out. That means C/C++ or a similar language, a Linux shell and the tools a verification team runs on. Expect long stretches parsing simulation output, working out why a run failed, and turning the findings into something a colleague can act on.
The AI in the title is AI-assisted tooling for test generation, analysis, debugging and documentation. Treat it as a layer on top of the scripting work. How much model building, if any, sits behind that is worth pinning down with the hiring team.
Early-career verification people with coding habits
The listing uses the word basic twice, once for Verilog/SystemVerilog and RTL/DV and again for UVM and the three interfaces. That reads as a role for someone a year or two in, or a strong fresher from an electronics or VLSI course who has run simulations and written testbenches. Fluent C/C++ counts for more here than depth in any single protocol.
Two profiles will struggle. A software engineer with no digital design exposure gets lost in the RTL and DV vocabulary. A verification engineer who has only clicked through a GUI testbench flow gets stuck on the scripting half. If you have both, even at a junior level, most of the ramp-up disappears.
Prepared from Quest Global's job posting and checked against it before publishing. See our Editorial Policy.
How to apply
- The Apply button opens this job on Quest Global's careers site (careers.quest-global.com).
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