Associate Engineer – AI/ML
Qualcomm — Bangalore
₹6–15 LPA (HireSetu estimate) · 1–2 yrs exp · Full-time · onsite
HireSetu listing reference 688030 — confirm requirements below, then apply on the employer site.
Quick answer: This is performance engineering work on Qualcomm's NPUs and GPUs, so the bar is embedded software plus chip architecture knowledge, with deep learning as the workload being measured.
From Qualcomm's job posting
Role overview
We are seeking a AI/ML Performance Engineer to drive performance analysis, optimization, and validation of AI workloads across Neural Processing Units (NPU),and GPUs in complex SoC platforms with a robust background in the field of deep learning (DL) to validate the performance of state-of-the-art low-level perception (LLP) as well as end-to-end AD models. The role focuses on AI/ML inference performance, latency, throughput, power efficiency, and system‑level integration, working closely with architecture, compiler, runtime, and framework teams. This position requires deep understanding of AI accelerator micro‑architecture, ML models, and end‑to‑end software stacks spanning drivers, runtimes, compilers, and frameworks.
Strong communication and interpersonal skills are required, and the candidate must be able to work effectively with various horizontal AI teams.
Minimum Qualifications
Bachelor's degree in Computer Science Engineering, Information Systems, or related field and 1+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience.
Skills
Good at software development with exposure to AI coding tools and excellent analytical, development, and problem-solving skills.
Experience in embedded software (Linux,Android,RTOS)
Experience in system performance domain with focus on neural accelerators and GPU
Knowledge on CPU, NPU,GPU, NOC , DDR architecture
Strong understanding of Machine Learning fundamentals
Knowledge in neural network quantization, compression, pruning algorithms, deep learning kernel/compiler optimization
Principal Duties and Responsibilities
Analyze and optimize AI/ML workload performance on NSP, NPU, and GPU across single and multi‑accelerator systems.
Identify bottlenecks across compute, memory bandwidth/latency, NoC, DMA, SMMU, and scheduling.
Drive optimizations for latency‑critical inference, high‑throughput pipelines, and concurrent multi‑VM execution.
Perform roofline, utilization, and memory access pattern analysis using hardware counters.
Benchmark and optimize CNNs, Transformers, VLMs, and diffusion models for real‑world and customer use cases.
Optimize model execution using operator fusion, graph partitioning, quantization, mixed precision, tiling, and batching.
Collaborate with system software teams on drivers, runtimes, memory allocation, power, thermal, and QoS constraints.
Analyze performance under concurrent, virtualized, and safety‑critical or real‑time environments.
Build and use benchmarks, micro‑benchmarks, profilers, and regression tools to derive actionable insights.
Partner with architecture, compiler, SDK, and AI framework teams to influence HW/SW design and resolve performance escalations.
Text from Qualcomm's official job posting, formatted by HireSetu. The employer's own page is the final word on details.
HireSetu's note
The job sits next to silicon
The title says AI/ML, and the daily work is working out why inference runs slower than it should on neural accelerators and GPUs. Training models is not part of it. You'll live in profilers, hardware counters and roofline plots, then trace the fix back to a kernel, a memory access pattern or a scheduling decision.
That is why the experience bar is 1 to 2 years and not zero. Freshers with coursework alone will find this steep. The listing wants someone who has already shipped embedded software on Linux, Android or an RTOS and can talk about CPU, GPU, NPU, NoC and DDR without hand-waving. A machine learning background works if you understand how kernels actually execute on hardware.
Lead your resume with measurements
Put the profiling and optimization work on the first page, with numbers. "Cut inference latency by 30% by fusing operators and moving to mixed precision" carries more weight than a list of frameworks. Roofline analysis, hardware counters and memory access patterns are the vocabulary here, so name the chip and the workload you measured.
Quantization, pruning and kernel or compiler optimization belong there too. If your embedded experience came from a different class of device, be explicit about what you profiled and how. When you get a call, ask which accelerators and which part of the stack you'd own, because that decides how much of the work is compiler-facing and how much is driver-facing.
Drafted with AI from Qualcomm's job posting and checked by Prashanth Jakkula before publishing. See our Editorial Policy.
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