Senior Staff- IP RTL Design Engineer

Marvell Technology — Bangalore

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. We are seeking a highly motivated RTL Design Engineer to architect and deliver next generation UCIe and high speed mixed signal IP. This role spans micro architecture definition through production quality RTL, with opportunities to act as both a strong individual contributor and a technical lead. What You Can Expect Responsibilities Architect, design, and implement state‑of‑the‑art RTL for UCIe/HBM and other high‑speed interface IP. Own micro‑architecture and RTL development for medium to high‑complexity digital blocks. Drive hands‑on execution including RTL coding, synthesis, CDC/RDC analysis, linting, debugging , and support for test and bring‑up. Partner closely with Architecture and Verification teams to define test plans, coverage strategies, and achieve verification closure. Participate in design reviews and contribute to IP quality, robustness, and r

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