Analog Mixed-Signal Verification Engineer

GlobalFoundries — IND - Karnataka - Bengaluru - North

Title: Analog Mixed-Signal Verification Engineer About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Job Overview: GlobalFoundries is seeking a highly motivated Mixed-Signal Verification Engineer to join our advanced design team. In this role, you will be instrumental in verifying complex analog and mixed-signal IP blocks and subsystems using GlobalFoundries cutting-edge semiconductor processes. You will develop and execute comprehensive AMS verification plans, including behavioral modeling of analog components using Verilog-A/AMS and SystemVerilog. Your responsibilities will include building and maintaining mixed-signal testbenches, performing co-simulation using industry-standard tools such as Spectre, Xcelium, and AMS Designer, and automating regression testing and coverage analysis to ensure robust verification outcomes. This role requires a basic understanding of analog design principles, verification methodologies, and cross-domain collaboration to achieve high-quality deliverables Essential Responsibilities : Develop and execute AMS verification plans for analog/mixed-signal Ips. Create behavioral models using Verilog-A/AMS and SystemVerilog. Build and maintain mixed-signal testbenches and perform co-simulation using industry-standard tools (Spectre, Xcelium, AMS Designer). Collaborate with design and layout teams to ensure verification coverage and post-silicon correlation. Automate regression testing and coverage analysis. Utilize tools such as Calibre, Synopsys CustomSim, and Cadence Virtuoso for PEX extraction, LVS/DRC signoff, and post-layout s

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