Staff Design Verification Engineering

Analog Devices — India, Bangalore, RMZ

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X . Job description: The Industrial Converter Technology group develops leading edge Signal Chain solutions for Industrial and other applications. The group is seeking a Staff AMS Verification Engineer who must have a proven track record of verifying complex mixed/digital signals ICs. The team handles verification of the products which include digital signal processing data-paths, sensors, high speed interfaces, and sub-systems. Candidate will work with the latest verification methodologies on designs ranging from individual blocks to sub-system level verification. Job Responsibilities: Define and develop block level/top level verification strategies based on design requirements and architecture. Experience with development of verification plan and verification environment from scratch on multiple projects. Should have worked on development of analog checkers, SV assertions, functional coverage, formal verification etc. to reach verification goals Specify, and perform as necessary, block and chip level RTL, gate, and mixed signal co-simulation regressions. Track progress against verification plan. Work with designers and product/apps engineers to achieve functional coverage goals and to debug the design and environment. Work closely with evaluation engineers when silicon arrives to compare and contrast simulation results Take complete ownership for complex feature verification and mentor ju

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